tilelang.transform.pass_config
==============================

.. py:module:: tilelang.transform.pass_config


Classes
-------

.. autoapisummary::

   tilelang.transform.pass_config.PassConfigKey


Module Contents
---------------

.. py:class:: PassConfigKey

   Bases: :py:obj:`str`, :py:obj:`enum.Enum`


   Pass configuration keys for TileLang compiler.


   .. py:attribute:: TL_SIMPLIFY
      :value: 'tl.Simplify'


      True

      :type: Enable/disable TileLang simplification passes. Default


   .. py:attribute:: TL_DYNAMIC_ALIGNMENT
      :value: 'tl.dynamic_alignment'


      16

      :type: Memory alignment requirement for dynamic shapes. Default


   .. py:attribute:: TL_DISABLE_DYNAMIC_TAIL_SPLIT
      :value: 'tl.disable_dynamic_tail_split'


      False

      :type: Disable dynamic tail splitting optimization. Default


   .. py:attribute:: TL_DISABLE_WARP_SPECIALIZED
      :value: 'tl.disable_warp_specialized'


      False

      :type: Disable warp specialization optimization. Default


   .. py:attribute:: TL_DISABLE_FAST_MATH
      :value: 'tl.disable_fast_math'


      False

      :type: Disable fast math optimization. Default


   .. py:attribute:: TL_PTXAS_REGISTER_USAGE_LEVEL
      :value: 'tl.ptxas_register_usage_level'


      The PTXAS register usage level in [0, 10], which controls the
      aggressiveness of optimizations that affect register usage. Default: None


   .. py:attribute:: TL_ENABLE_PTXAS_VERBOSE_OUTPUT
      :value: 'tl.enable_ptxas_verbose_output'


      False

      :type: Enable ptxas verbose output. Default


   .. py:attribute:: TL_CONFIG_INDEX_BITWIDTH
      :value: 'tl.config_index_bitwidth'


      32

      :type: Bitwidth for configuration indices. Default


   .. py:attribute:: TL_DISABLE_TMA_LOWER
      :value: 'tl.disable_tma_lower'


      False

      :type: Disable TMA (Tensor Memory Access) lowering. Default


   .. py:attribute:: TL_DISABLE_SAFE_MEMORY_ACCESS
      :value: 'tl.disable_safe_memory_legalize'


      False

      :type: Disable safe memory access optimization. Default


   .. py:attribute:: TL_DEBUG_MERGE_SHARED_MEMORY_ALLOCATIONS
      :value: 'tl.debug_merge_shared_memory_allocations'


      False

      :type: Enable debug information for merge shared memory allocations. Default


   .. py:attribute:: TL_ENABLE_AGGRESSIVE_SHARED_MEMORY_MERGE
      :value: 'tl.enable_aggressive_shared_memory_merge'


      False

      :type: Enable aggressive merge of shared memory allocations. Default


   .. py:attribute:: TIR_ENABLE_EQUIV_TERMS_IN_CSE
      :value: 'tir.enable_equiv_terms_in_cse_tir'


      True

      :type: Enable equivalent terms in TIR Common Subexpression Elimination. Default


   .. py:attribute:: TIR_DISABLE_CSE
      :value: 'tir.disable_cse_tir'


      False

      :type: Disable TIR Common Subexpression Elimination. Default


   .. py:attribute:: TIR_SIMPLIFY
      :value: 'tir.Simplify'


      True

      :type: Enable/disable TIR simplification passes. Default


   .. py:attribute:: TIR_DISABLE_STORAGE_REWRITE
      :value: 'tir.disable_storage_rewrite'


      False

      :type: Disable storage rewrite optimization. Default


   .. py:attribute:: TIR_DISABLE_VECTORIZE
      :value: 'tir.disable_vectorize'


      False

      :type: Disable vectorization optimization. Default


   .. py:attribute:: TIR_USE_ASYNC_COPY
      :value: 'tir.use_async_copy'


      True

      :type: Enable asynchronous memory copy operations. Default


   .. py:attribute:: TIR_ENABLE_DEBUG
      :value: 'tir.enable_debug'


      False

      :type: Enable debug information in generated code. Default


   .. py:attribute:: TIR_MERGE_STATIC_SMEM
      :value: 'tir.merge_static_smem'


      True

      :type: Merge static shared memory allocations. Default


   .. py:attribute:: TIR_ADD_LOWER_PASS
      :value: 'tir.add_lower_pass'


      None

      :type: Additional lowering passes to be applied. Default


   .. py:attribute:: TIR_NOALIAS
      :value: 'tir.noalias'


      True

      :type: Enable pointer non-aliasing assumptions. Default


   .. py:attribute:: CUDA_KERNELS_OUTPUT_DIR
      :value: 'cuda.kernels_output_dir'


      empty string

      :type: Output directory for generated CUDA kernels. Default